Chipyard 架構之後量子密碼簽章開源平台實作與效能分析：以 SPHINCS+ 為例

Abstract

隨著量子計算技術的迅速進展，傳統公鑰密碼系統將面臨被破解的潛在風險。SPHINCS+ 是一種基於雜湊函數的後量子數位簽章演算法，具備對量子計算攻擊的抵抗能力。SPHINCS+ 演算法允許私鑰重複使用且無需追蹤使用次數，兼具高度安全性與可預測性，特別適合應用於對資訊安全具有高度要求的嵌入式裝置。然而，SPHINCS+ 本身計算過程複雜且速度慢，對於資源受限系統構成明顯的效能瓶頸。 為解決此問題，本研究採用開源 RISC-V SoC 設計平台 Chipyard，整合 Rocket Core 處理器與 RoCC（Rocket Custom Coprocessor）硬體協同處理器介面， 導入 SHA3 開源硬體加速器以提升關鍵雜湊運算效率，實現 RISC-V 後量子密碼 硬體架構。系統架構中結合 SPHINCS+ 中的三種簽章演算法：FORS、WOTS+ 與 多層 Merkle Tree，進行軟硬體整合設計，聚焦於 SHA3 雜湊運算之硬體加速優化。 實驗結果顯示所提出的硬體加速設計可顯著降低 SPHINCS+ 簽章生成與驗證延 遲，同時透過參數集調整，使其更適用應用於嵌入式系統實際部署，達成高效且安 全之後量子密碼簽章實作。With the rapid advancement of quantum computing technology, traditional publickey cryptographic systems are increasingly vulnerable to potential quantum-basedattacks. SPHINCS+, a stateless hash-based post-quantum digital signature scheme, isdesigned to resist such threats. It offers the advantage of allowing private key reusewithout the need for state tracking, thus providing a high levels of security andpredictability. These features make SPHINCS+ particularly suitable for embeddedsystems with stringent information security requirements. However, SPHINCS+ incurssubstantial computational overhead, resulting in performance bottlenecks in resourceconstrained environments.This study adopts Chipyard, an open-source RISC-V SoC design framework, andintegrates the Rocket Core processor with the RoCC (Rocket Custom Coprocessor)interface. A SHA3 hardware accelerator is incorporated to enhance the efficiency of hashcomputations, enabling the realization of a RISC-V-based post-quantum cryptographichardware architecture. The proposed system design integrates three core components ofSPHINCS+: FORS, WOTS+, and multi-layer Merkle trees, through a hardware/softwareco-design approach that focuses on SHA3 acceleration. Experimental results demonstratethat the hardware-accelerated implementation significantly reduces the latency ofSPHINCS+ signature generation and verification. Furthermore, by tuning securityparameters, the system is optimized for practical deployment in embedded platforms,achieving both high performance and strong post-quantum security.